vm_dcl_spi_config_parameter

Syntax

typedef struct {
  VMUINT32 cs_setup_time;
  VMUINT32 cs_hold_time;
  VMUINT32 cs_idle_time;
  VMUINT32 clock_low_time;
  VMUINT32 clock_high_time;
  VM_DCL_SPI_MSBF tx_msbf;
  VM_DCL_SPI_MSBF rx_msbf;
  VM_DCL_SPI_ENDIAN tx_endian;
  VM_DCL_SPI_ENDIAN rx_endian;
  VM_DCL_SPI_CLOCK_POLARITY clock_polarity;
  VM_DCL_SPI_CLOCK_PHASE clock_phase;
} vm_dcl_spi_config_parameter_t;

Description

vm_dcl_spi_config_parameter_t holds the SPI configuration parameters.

Example

 VM_DCL_HANDLE spi_handle;
 vm_dcl_spi_config_parameter_t config_data;
spi_handle = vm_dcl_open(VM_DCL_SPI_PORT1,0);
if(VM_DCL_HANDLE_INVALID==spi_handle) return;
 config_data.clock_high_time = 5;
 config_data.clock_low_time = 5;
 config_data.cs_hold_time = 15;
 config_data.cs_idle_time = 15;
 config_data.cs_setup_time= 15;
 config_data.clock_polarity = VM_DCL_SPI_CLOCK_POLARITY_0;
 config_data.clock_phase = VM_DCL_SPI_CLOCK_PHASE_0;
 config_data.rx_endian = VM_DCL_SPI_ENDIAN_LITTLE;
 config_data.tx_endian = VM_DCL_SPI_ENDIAN_LITTLE;
 config_data.rx_msbf = VM_DCL_SPI_MSB_FIRST;
 config_data.tx_msbf = VM_DCL_SPI_MSB_FIRST;
 vm_dcl_control(spi_handle,VM_DCL_SPI_CONTROL_SET_CONFIG_PARAMETER,(void *)&config_data);
//To do something.

File

vmdcl_spi.h

Members

Members	Description
VMUINT32 cs_setup_time;	The CS setup time. Unit in SPI base clock count. Range(0-255). The chip select setup time = (cs_setup_time+1)*clock_PERIOD, where clock_PERIOD is the cycle time of the clock that the SPI engine adopts.
VMUINT32 cs_hold_time;	The CS hold time. Unit in SPI base clock count. Range(0-255). The chip select hold time = (cs_hold_time+1)*clock_PERIOD.
VMUINT32 cs_idle_time;	The CS idle time. Unit in SPI base clock count. Range(0-255). The chip select idle time between consecutive transaction = (cs_idle_time+1)*clock_PERIOD.
VMUINT32 clock_low_time;	The SCK clock low time. Unit in SPI base clock count Range(0-255).
VMUINT32 clock_high_time;	The SCK clock high time. Unit in SPI base clock count. Range(0-255).
VM_DCL_SPI_MSBF tx_msbf;	The bit order setting for SPI output.
VM_DCL_SPI_MSBF rx_msbf;	The bit order setting for SPI input.
VM_DCL_SPI_ENDIAN tx_endian;	The byte order setting for SPI output.
VM_DCL_SPI_ENDIAN rx_endian;	The byte order setting for SPI input.
VM_DCL_SPI_CLOCK_POLARITY clock_polarity;	The SPI clock polarity.
VM_DCL_SPI_CLOCK_PHASE clock_phase;	The SPI clock format.

Group

Structs, Records, Enums

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